| PART |
Description |
Maker |
| 74LCX112SJ 74LCX112 74LCX112M 74LCX112MTC 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
Fairchild Semiconductor, Corp.
http://
FAIRCHILD[Fairchild Semiconductor]
|
| LT1033 LT1033C LT1033CK LT1033M LT1033MK |
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SO 0 to 70
3A. Negative Adjustable Regulator
3A, Negative Adjustable Regulator
From old datasheet system
|
Linear Technology Corporation
LINER[Linear Technology]
|
| SN74LS73N |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
Motorola
|
| 74ALS112AD 74ALS112AN 74ALS112 74ALS112A |
Dual J-K negative edge-triggered flip-flop
|
NXP Semiconductors
PHILIPS[Philips Semiconductors]
|
| 74LS112 DM74LS112A DM74LS112AN DM74KS112AM |
From old datasheet system
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs
|
FAIRCHILD[Fairchild Semiconductor]
|
| 74F113 I74F113D I74F113N N74F113D N74F113N 74F113_ |
From old datasheet system
Dual J-K negative edge-triggered flip-flops without reset
|
NXP Semiconductors
PHILIPS[Philips Semiconductors]
|
| 74LS73PC |
LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
|
FAIRCHILD SEMICONDUCTOR CORP
|
| IDT74LVC11 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O
|
IDT
|
| 74ACT11112 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 具有清零和预设功能的双路 J-K 下降沿触发器
|
Linear Technology, Corp.
|
| ACTS112HMSR-02 |
ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16
|
HARRIS SEMICONDUCTOR
|
| CD74HCT107E CD74HC107M96 CD74HC107MT |
<font color=red>[Old version datasheet]</font> Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
TI store
|
